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Toshiba TMPR4955B Full Processor Specifications

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Generel Characteristics

Designer

Toshiba

Type

TMPR4955B

Codename

TX4955B

Year Released

2002

Function

Application Processor

Architecture

Width of Machine Word

64 bit

Supported Instruction Set(s)

MIPS I, MIPS II, MIPS III

Number of processor core(s)

Type of processor core(s)

MIPS R4000 (Toshiba TX49/H3)

Buses

Memory Interface(s)

Yes

Data Bus Width

64 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Internal Systembus Clock

120 MHz

Recommended Maximum Clock Frequency

N/A

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Technology and Packaging

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

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Texas Instruments OMAP V1030

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Philips PR31100

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