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Philips PR31100 Full Processor Specifications

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Generel Characteristics

Designer

Philips

Type

PR31100

Codename

Poseidon

Year Released

1996

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

MIPS I, MIPS II

Number of processor core(s)

Type of processor core(s)

MIPS R3000A

Buses

Memory Interface(s)

Yes

Data Bus Width

32 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Internal Systembus Clock

20 MHz

Recommended Maximum Clock Frequency

40 MHz max.

Cache Memories

L1 Instruction Cache per Core

4 Kbyte I-Cache

L1 Data Cache per Core

1 Kbyte D-Cache

Technology and Packaging

Semiconductor Technology

CMOS

Number of Transistors Integrated

110000

Supply Voltage

3.3 V

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

Bus Interface Unit

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Toshiba TMPR4955B

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Marvell PXA310

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