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SiRF titan GPS V5 Full Processor Specifications

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Generel Characteristics

Designer

SiRF

Type

titan GPS V5

Year Released

2007

Function

System-On-a-Chip

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv6

Pipeline Stages

8 pipeline stages

Number of processor core(s)

Type of processor core(s)

ARM1136EJ-S

Buses

Memory Interface(s)

SDRAM

Data Bus Width

64 bit

Number of data bus channels

1 ch

Non-volatile Memory Data Bus Width

16 bit

Non-volatile Memory Interface

Yes

DMA Channels

16 ch

Clock Frequencies

Recommended Minimum Clock Frequency

600 MHz min.

Recommended Maximum Clock Frequency

650 MHz max.

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

16 Kbyte D-Cache

Total L2 Cache

128 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Pins

477 pins

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Yes

Additional Information

Special Features

16-channel DMA, VFPU, AMBA 2.0 AHB, ARM Jazelle, integrated 40+ channels Centrality GPS V5 DSP

Disclaimer: DeviceBeast can not guarantee that the information on this page is 100% correct

Devices Using SiRF titan GPS V5

Blaupunkt TravelPilot 500 Specifications

Navigon 7300 / 7310 Specifications

Blaupunkt TravelPilot 700 Specifications

Previous Processor

Centrality Titan GPS V5

Next Processor

Telechip TCC8902

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