Centrality Titan GPS V5 Full Processor Specifications
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Generel Characteristics
Centrality
Titan GPS V5
2007
System-On-a-Chip
Architecture
32 bit
ARMv6
8 pipeline stages
1
ARM1136EJ-S
Buses
SDRAM , DDR SDRAM
32 bit
1 ch
32 bit
Yes
Clock Frequencies
600 MHz min.
650 MHz max.
Cache Memories
16 Kbyte I-Cache
16 Kbyte D-Cache
128 Kbyte L2
Technology and Packaging
CMOS
477 pins
Graphical Subsystem
N/A
Cellular Communication
No
Satellite Navigation
Yes
Additional Information
MMU, AMBA 2.0 AHB, ARM Jazelle, VFPU, integrated 40+ channels Centrality GPS V5 DSP
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Devices Using Centrality Titan GPS V5
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