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NEC VR5500 Full Processor Specifications

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Generel Characteristics

Designer

NEC

Type

VR5500

Year Released

2001

Function

Application Processor

Architecture

Width of Machine Word

64 bit

Supported Instruction Set(s)

MIPS I, MIPS II, MIPS III, MIPS IV

Number of processor core(s)

Type of processor core(s)

MIPS R5000 (NEC VR5500)

Buses

Memory Interface(s)

Yes

Data Bus Width

64 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Internal Systembus Clock

300 MHz

Recommended Maximum Clock Frequency

N/A

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

1024 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Number of Transistors Integrated

3700000

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

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