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NEC VR4305 Full Processor Specifications

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Generel Characteristics

Designer

NEC

Type

VR4305

Year Released

1998

Function

Application Processor

Architecture

Width of Machine Word

64 bit

Supported Instruction Set(s)

MIPS I, MIPS II, MIPS III

Pipeline Stages

5 pipeline stages

Number of processor core(s)

Type of processor core(s)

MIPS R4300i

Buses

Memory Interface(s)

Yes

Data Bus Width

64 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Internal Systembus Clock

33 MHz

Recommended Maximum Clock Frequency

N/A

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

8 Kbyte D-Cache

Total L2 Cache

1024 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Pins

120 pins

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

5-stage Pipeline

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