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ARM 1156T2F-S Full Processor Specifications

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Generel Characteristics

Designer

ARM

Type

1156T2F-S

Year Released

2003

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv6T2

Pipeline Stages

8 pipeline stages

Number of processor core(s)

Type of processor core(s)

ARM1156

Buses

Memory Interface(s)

Yes

Data Bus Width

32 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Recommended Minimum Clock Frequency

320 MHz min.

Recommended Maximum Clock Frequency

620 MHz max.

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

16 Kbyte D-Cache

Technology and Packaging

Feature Size

90 nm

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

Configurable cache sizes, 32 bit addressing, MPU, AMBA 3.0 AXI bus, DSP Instruction Set Extensions, Vector Floating Point coprocessor

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