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ZiiLABS ZMS-08 Full Processor Specifications

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Generel Characteristics

Designer

ZiiLABS

Type

ZMS-08

Year Released

2009

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv7

Pipeline Stages

13 pipeline stages

Number of processor core(s)

Type of processor core(s)

ARM Cortex-A8

Buses

Memory Interface(s)

SDRAM , DDR SDRAM , mobile (LP) DDR SDRAM , DDR2 SDRAM

Data Bus Width

64 bit

Number of data bus channels

1 ch

Non-volatile Memory Data Bus Width

32 bit

Non-volatile Memory Interface

NAND Flash Interface , NOR Flash Interface

Clock Frequencies

Recommended Maximum Clock Frequency

1000 MHz max.

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

256 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Pins

434 pins

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

SIMD Media Processing Array (64 Precessing elements), Xtreme Fidelity X-Fi Audio Processing, Dual USB 2.0, Dual USB 2.0 OTG controllers with on-chip PHY and ULPI interfaces, Three SD/SDIO/MMC/CE-ATA controllers, Dual high fidelity digital audio ports, I2S/PCM, I2C, 5 UARTs, 113 GPIOs, Hi-Speed Serial Input, Flexible General Interface Bus, PLLs, OpenGL ES 1.1 and 2.0 3D graphics, Four Independent, Bi-directional HD Capable Video Ports, Connect to LCDs up to 24-bit, Connect to Multiple High Resolution Cameras, Integrated Analog HD TV encoder, Intergrated HDMI transmitter

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