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Toshiba TMPR3922U Full Processor Specifications

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Generel Characteristics

Designer

Toshiba

Type

TMPR3922U

Year Released

1998

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

MIPS I, MIPS II

Number of processor core(s)

Type of processor core(s)

MIPS R3000A (Toshiba TX3920)

Buses

Memory Interface(s)

Yes

Data Bus Width

32 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Internal Systembus Clock

66 MHz

Recommended Maximum Clock Frequency

N/A

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

8 Kbyte D-Cache

Technology and Packaging

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

32MB DRAM / 64MB ROM addressing

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