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Texas Instruments OMAP 3525 Full Processor Specifications

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Generel Characteristics

Designer

Texas Instruments

Type

OMAP 3525

Year Released

2009

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv7

Pipeline Stages

13 pipeline stages

Number of processor core(s)

Type of processor core(s)

ARM Cortex-A8

Buses

Memory Interface(s)

mobile (LP) DDR SDRAM

Data Bus Width

32 bit

Number of data bus channels

1 ch

Non-volatile Memory Data Bus Width

16 bit

Non-volatile Memory Interface

NAND Flash Interface , NOR Flash Interface , OneNAND

DMA Channels

64 ch

Clock Frequencies

Recommended Maximum Clock Frequency

720 MHz max.

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

16 Kbyte D-Cache

Total L2 Cache

256 Kbyte L2

Technology and Packaging

Feature Size

65 nm

Semiconductor Technology

CMOS

Fab

Texas Instruments

Pins

515 pins

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

NEON SIMD Coprocessor, 64-Ch EDMA, 32-Ch sDMA controller, asynchs SRAM support, IVA2.2 Accelerator Subsystemem (embedded 430MHz VLIW TI TMS320C64x+ DSP), embedded image signal processor, 112Kbyte ROM, 64Kbyte SRAM, ARM TrustZone, Composite and S-video TV output, SmartReflex Technology, High Speed USB 2.0 On-The-Go support

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