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SiRF atlasIV Full Processor Specifications

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Generel Characteristics

Designer

SiRF

Type

atlasIV

Year Released

2009

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv6

Pipeline Stages

8 pipeline stages

Number of processor core(s)

Type of processor core(s)

ARM1136JF-S

Buses

Memory Interface(s)

SDRAM , mobile (LP) DDR SDRAM , DDR2 SDRAM

Data Bus Width

64 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

NAND Flash Interface

DMA Channels

16 ch

Clock Frequencies

Recommended Maximum Clock Frequency

500 MHz max.

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

16 Kbyte D-Cache

Technology and Packaging

Feature Size

65 nm

Semiconductor Technology

CMOS

Pins

292 pins

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Yes

Additional Information

Special Features

16-channel DMA, VFPU, integrated 64-channel SiRF GPS engine, TCM 16 KB/16 KB

Disclaimer: DeviceBeast can not guarantee that the information on this page is 100% correct

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