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NEC VR4200 Full Processor Specifications

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Generel Characteristics

Designer

NEC

Type

VR4200

Year Released

1994

Function

Application Processor

Architecture

Width of Machine Word

64 bit

Supported Instruction Set(s)

MIPS I, MIPS II, MIPS III, MIPS16

Pipeline Stages

5 pipeline stages

Number of processor core(s)

Type of processor core(s)

MIPS R4200

Buses

Memory Interface(s)

Yes

Data Bus Width

64 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Internal Systembus Clock

100 MHz

Recommended Maximum Clock Frequency

N/A

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

8 Kbyte D-Cache

Technology and Packaging

Feature Size

600 nm

Semiconductor Technology

CMOS

Number of Transistors Integrated

1300000

Pins

179 pins

Supply Voltage

3.3 V

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

5-stage Pipeline

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