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Marvell Armada 610 Full Processor Specifications

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Generel Characteristics

Designer

Marvell

Type

Armada 610

Year Released

2010

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv7

Number of processor core(s)

Type of processor core(s)

Marvell Sheeva

Buses

Memory Interface(s)

DDR SDRAM , mobile (LP) DDR SDRAM , mobile (LP) DDR2 SDRAM

Data Bus Width

32 bit

Number of data bus channels

1 ch

Non-volatile Memory Data Bus Width

16 bit

Non-volatile Memory Interface

NAND Flash Interface

Clock Frequencies

Recommended Maximum Clock Frequency

1000 MHz max.

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

256 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

Marvell Sheeva Superscalar processor core, VFPUv3, WMMX2, 8/16-bit eMMC (SLC/MLC) NAND Flash support, integrated 2D/3D GPU, 1080p H.264 30fps decode, 1080p 30fps H.264 encode, USB 2.0 host, USB 2.0 OTG, HDMI v1.3a TV out support, ISP, 16 MP camera support

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