Share This Processor

Ingenic M200 Full Processor Specifications

You are currently previewing Ingenic M200 processor specifications. View all our processor list for other models.

Generel Characteristics

Designer

Ingenic

Type

M200

Year Released

2015

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

MIPS32

Pipeline Stages

9 pipeline stages

Number of processor core(s)

Type of processor core(s)

1x MIPS XBurst-HP + 1x MIPS XBurst-LP

Buses

Memory Interface(s)

mobile (LP) DDR SDRAM , DDR2 SDRAM , mobile (LP) DDR2 SDRAM , DDR3 SDRAM

Max. Clock Frequency of Memory IF

667 MHz

Data Bus Width

32 bit

Number of data bus channels

1 ch

Max. Data Rate

5.34 Gbyte/s

Non-volatile Memory Data Bus Width

64 bit

Non-volatile Memory Interface

NAND Flash Interface

DMA Channels

32 ch

Clock Frequencies

Recommended Maximum Clock Frequency

1200 MHz max.

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

512 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Pins

270 pins

Graphical Subsystem

Embedded GPU

N/A

Number of GPU cores

1-core GPU

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

1x XBurst-HP (1.2GHz) + 1x XBurst-LP (300 MHz) cores, SIMD instruction set, 16/32-bit SD RAM interface, 64-bit ECC NAND flash support, 512B/2KB/4KB/8KB/16KB page size, Xburst VPU, OpenGL ES2.0 and ES1.1, OpenVG1.1, 720p 30 fps video encode, 720p 30 fps video decode, AC97/I2S/SPDIF, Audio Codec, LCD interface, ISP, USB 2.0 OTG.

Disclaimer: DeviceBeast can not guarantee that the information on this page is 100% correct