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HiSilicon K3V2 Hi3620 poster

HiSilicon K3V2 Hi3620 Full Processor Specifications

You are currently previewing HiSilicon K3V2 Hi3620 processor specifications. View all our processor list for other models.

Generel Characteristics

Designer

HiSilicon

Type

K3V2 Hi3620

Year Released

2012

Function

Multi-core Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv7

Pipeline Stages

8 pipeline stages

Number of processor core(s)

4

Type of processor core(s)

4x ARM Cortex-A9 MPcore

Buses

Memory Interface(s)

mobile (LP) DDR2 SDRAM

Max. Clock Frequency of Memory IF

450 MHz

Data Bus Width

32 bit

Number of data bus channels

2 ch

Max. Data Rate

7.2 Gbyte/s

Non-volatile Memory Interface

NAND Flash Interface

Clock Frequencies

Recommended Minimum Clock Frequency

1200 MHz min.

Recommended Maximum Clock Frequency

1500 MHz max.

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

1024 Kbyte L2

Technology and Packaging

Feature Size

40 nm

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

Vivante GC4000 GPU

Number of GPU cores

16-core GPU

GPU Clock

480 MHz GPU

Cellular Communication

Supported Cellular Data Links

No

Satellite Navigation

Supported GPS protocol(s)

No

Additional Information

Special Features

quad ARM Cortex-A9 Superscalar processor cores, 1080p30 video encode, 1080p60 video decode, 20 MP camera support

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Devices Using HiSilicon K3V2 Hi3620

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