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HiSilicon K3V1 Hi3611 Full Processor Specifications

You are currently previewing HiSilicon K3V1 Hi3611 processor specifications. View all our processor list for other models.

Generel Characteristics

Designer

HiSilicon

Type

K3V1 Hi3611

Codename

Year Released

2009

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv5TEJ

Number of processor core(s)

Type of processor core(s)

ARM926EJ-S

Buses

Memory Interface(s)

SDRAM , mobile (LP) DDR SDRAM

Data Bus Width

16 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

NAND Flash Interface , NOR Flash Interface

Clock Frequencies

Recommended Minimum Clock Frequency

360 MHz min.

Recommended Maximum Clock Frequency

460 MHz max.

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

16 Kbyte D-Cache

Technology and Packaging

Feature Size

130 nm

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

N/A

Number of GPU cores

1-core GPU

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

Graphics Engine, 200KB shared SRAM, RawNAND / NOR / DoC Flash interface, ARM Jazelle

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Devices Using HiSilicon K3V1 Hi3611

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