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Freescale i.MX535D VV2C Full Processor Specifications

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Generel Characteristics

Designer

Freescale

Type

i.MX535D VV2C

Codename

MCIMX535DVV2C

Year Released

2011

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv7

Pipeline Stages

13 pipeline stages

Number of processor core(s)

Type of processor core(s)

ARM Cortex-A8

Buses

Memory Interface(s)

DDR2 SDRAM , mobile (LP) DDR2 SDRAM , DDR3 SDRAM

Max. Clock Frequency of Memory IF

400 MHz

Data Bus Width

32 bit

Number of data bus channels

1 ch

Max. Data Rate

3.2 Gbyte/s

Non-volatile Memory Data Bus Width

16 bit

Non-volatile Memory Interface

NOR Flash Interface

DMA Channels

1 ch

Clock Frequencies

Recommended Minimum Clock Frequency

800 MHz min.

Recommended Maximum Clock Frequency

1200 MHz max.

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

256 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Fab

Freescale

Pins

529 pins

Supply Voltage

1.4 V

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

128KB shared SRAM, MMU, Smart DMA, ARM NEON SIMD engine, ARM TrustZone, 64-bit AMBA AXI v1.0 bus, 32-bit AMBA AHB 2.0 bus, vector floating point (VFP-Lite), 16/32-bit DDR2-800, LV-DDR2-800, DDR3-800, 32-bit LPDDR2 RAM interface, 8/16-bit NAND SLC/MLC Flash , 4/8/14/16-bit ECC, 8/16-bit NOR Flash, PSRAM, and cellular RAM interface, GPU3D 3D graphics processing unit (256 Kbyte RAM), OpenGL ES 2.0, GPU2D 2D graphics accelerator, OpenVG 1.1, PATA, SATA interface, HDMI interface (1080p60), SPDIF, 10/100 Ethernet controller

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