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DEC StrongARM SA-1100 Full Processor Specifications

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Generel Characteristics

Designer

DEC

Type

StrongARM SA-1100

Year Released

1997

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv4

Number of processor core(s)

Type of processor core(s)

ARM SA-1

Buses

Memory Interface(s)

EDO DRAM , SDRAM

Data Bus Width

32 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

NOR Flash Interface

Clock Frequencies

Internal Systembus Clock

66 MHz

Recommended Maximum Clock Frequency

190 MHz max.

Cache Memories

L1 Instruction Cache per Core

16 Kbyte I-Cache

L1 Data Cache per Core

8 Kbyte D-Cache

Technology and Packaging

Feature Size

350 nm

Semiconductor Technology

CMOS

Number of Transistors Integrated

2500000

Pins

208 pins

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

embedded flash ROM, FPM / EDO DRAM / SDRAM / SRAM interface, flash ROM / ROM interface, MMU, Write buffer, Read buffer, LCD controller, serial I/O, PCMCIA controller

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