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ARM Cortex-A12 MPCore Full Processor Specifications

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Generel Characteristics

Designer

ARM

Type

Cortex-A12 MPCore

Year Released

2013

Function

Multi-core Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv7-A

Number of processor core(s)

Type of processor core(s)

4x ARM Cortex-A12 MPcore

Buses

Memory Interface(s)

Yes

Data Bus Width

128 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

Clock Frequencies

Recommended Maximum Clock Frequency

2500 MHz max.

Cache Memories

L1 Instruction Cache per Core

64 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

8192 Kbyte L2

Technology and Packaging

Feature Size

28 nm

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

N/A

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

up to 4x Cortex-A12 Harvard Superscalar processor core, Configurable per processor L1 (32 or 64 Kbyte I-cache, 32 Kbyte D-cache) and common L2 (256 Kbyte ... 8 Mbyte) cache sizes, VFPv4 FPU, ARMv7 MMU, SCU, LPAE, 128bit AMBA 4 AXI Bus, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight SoC-400, ARM Jazelle RCT + DBX

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