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Allwinner A10 Full Processor Specifications

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Generel Characteristics

Designer

Allwinner

Type

A10

Year Released

2012

Function

Application Processor

Architecture

Width of Machine Word

32 bit

Supported Instruction Set(s)

ARMv7

Pipeline Stages

13 pipeline stages

Number of processor core(s)

Type of processor core(s)

ARM Cortex-A8

Buses

Memory Interface(s)

mobile (LP) DDR2 SDRAM , mobile (LP) DDR3 SDRAM

Data Bus Width

32 bit

Number of data bus channels

1 ch

Non-volatile Memory Interface

NAND Flash Interface

Clock Frequencies

Recommended Maximum Clock Frequency

N/A

Cache Memories

L1 Instruction Cache per Core

32 Kbyte I-Cache

L1 Data Cache per Core

32 Kbyte D-Cache

Total L2 Cache

256 Kbyte L2

Technology and Packaging

Semiconductor Technology

CMOS

Graphical Subsystem

Embedded GPU

ARM Mali-400 GPU

Dedicated Graphics Memory

0.25 MiB

Cellular Communication

Supported Cellular Data Links

Satellite Navigation

Supported GPS protocol(s)

Additional Information

Special Features

ARM Cortex-A8 Harvard Superscalar processor core, 32-bit LP-DDR2 / LP-DDR3 memory interface, ARM Mali-400 GPU, ARM Jazelle, ARM TrustZone, OpenGL ES 2.0, 1080p display support, 2160p video decode, 1080p video encode, HDMI 1.4, USB 2.0 OTG, USB host, Android 4.2 support

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